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Cadence offers IC design solutions for fan-out wafer-level chip scale packaging

PKBR Staff Writer Published 15 March 2016

Cadence Design Systems is offering complete IC packaging design and analysis solutions for advanced fan-out wafer-level chip scale packaging (WLCSP) and 2.5D interposer-based designs.

Designed to accelerate the multi-chip integration for smaller, lighter and power-optimized wireless mobile devices, the IC packaging design and analysis solution includes the Cadence OrbitIO Interconnect Designer, Cadence System-in-Package (SiP) Layout and Cadence Physical Verification System (PVS).

Cadence PCB Group senior product engineering group director Steve Durrill said: "Our latest release enables broad WLCSP-enabled design and foundry and OSAT manufacturing signoff, which in turn helps fabless semiconductor and systems companies deliver ultra-thin mobile-focused devices using the latest foundry and OSAT IC package manufacturing approaches."

Cadence said that the solutions allow multi-substrate interconnect pathway design, refinement, implementation and manufacturing verification and signoff spanning die I/O pad rings through IC package to system PCB.

Integrated with PVS provides generic silicon wafer-based packaging methodologies, the new Cadence SiP Layout WLCSP option has been validated by TSMC for their integrated fan-out (InFO) process earlier.

Additionally, OrbitIO Interconnect Designer has been enhanced to strengthen 2.5D interposer package design support.

In addition to providing optimal multi-die, single package interconnect integration, the OrbitIO Interconnect Designer enhancements enable higher performance for multi-substrate integrated devices with minimal size optimized for signal performance.